Power supply decoupling is the term given to the technique of making sure the DC power line variations do not affect the loads (amplifier, ICs, logic gates, etc.) and vice versa. Since most ICs have AC signals as inputs and outputs, the current drawn from the power supply will vary in an AC manner. For example, an RF circuit that amplifies a 900 MHz signal will draw a supply current that varies at 900 MHz. A digital CMOS circuit that buffers a 100 MHz digital signal will also draw a supply current that varies at 100 MHz. For digital CMOS circuits, the vast majority of the current occurs during the transitions between the high and low voltages. Therefore the edges of digital signals can create very short time periods of high current demand. Power supply circuits themselves can only handle relatively low-frequency current variations. A typical power supply can track variations of from several hundred to several thousand Hertz. Furthermore, due to the physical distance between the supply and the circuit load, varying currents can propagate along the supply lines. The varying currents cause the voltage of the supply to sag and surge. If the voltage of the supply varies too greatly, the IC that is using the supply will not function properly. A second result is that the supply voltage becomes modulated. The supply modulations travel to other ICs, and signals then couple from one IC to another through the supply. To address these problems, the supply and loads are decoupled from each other by placing capacitors across the supply and ground.
Power supply decoupling has two related goals: charge supply and filtering. The charge stored on the decoupling capacitors serves as a reservoir that is quickly accessible for load variations. Each circuit has an effective impedance that it presents to the power supply; that is, each circuit acts like a load to the power supply. This impedance is not constant, but depends on the signals that the circuit processes. The circuit will have a DC (quiescent) supply impedance and a variable supply impedance. When a power distribution system is properly designed, the
Figure 12.10 Power supply filtering.
decoupling capacitors provide charge for the variations in the circuit loads such that each circuit receives a constant supply voltage at all times.
The second goal or function of power supply decoupling is filtering. All switch-mode power supplies are inherently noisy. Furthermore, any product powered form the 60 Hz mains voltage will receive noise conducted through the power line. Decoupling capacitors serve to shunt this noise to ground. Voltages from signal traces and from ICs can also couple to the power supply through conductive pathways or by near-field coupling. Decoupling serves to shunt these voltages to ground, maintaining a constant DC voltage on the supply. Some circuits require more than just capacitors to provide proper filtering. Very sensitive circuits such as analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) require LC filters to filter the power supply. The best filter topology for this application is that of a pi low-pass filter, as shown in Figure 12.10.
A ferrite bead can be used in place of or in conjunction with the inductor in this circuit. Often the first capacitor in the filter is not explicitly used, but is provided by other decoupling capacitors on the power supply. However, never omit the second capacitor (the load side capacitor), and don't use a T low-pass filter, because such filters will not provide a proper charge reservoir to the load. (The source side capacitor's charge is impeded by the inductor.) LC filters can also be used at the power supply output and at the power entry point to the product. A similar filter arrangement is used in most RF amplifiers. In these applications, the inductor is referred to as an RF choke. The circuit is essentially the same. Clocks and phase lock loops (PLL) also typically require an LC filter to prevent the large oscillations from coupling to the power supply. In low-frequency analog circuits, such as op-amp circuits, the power supply is sometimes filtered with an RC low-pass filter. The resistor lowers the voltage the op-amp receives, so its value must be small (10 W to 100 W) to avoid a large voltage drop.
To maximize its utility as a charge storage device, you want to maximize the charge-to-volt ratio of the capacitor, Q/V = C. To maximize its performance as a filtering element, you want to minimize the impedance, Z = 1/jwC. Both of these goals are attained by maximizing the capacitance, C. Using huge capacitors seems to be a perfect solution. Unfortunately, decoupling is not that simple. Part of the problem stems from the parasitic elements of capacitors, as discussed in Chapter 7. Any real capacitor has a series resistance (ESR) and series inductance (ESL). ESL is mostly a function of package size. Large capacitors need large packages and thus larger inductance results. ESR is mostly a function of the dielectric material. Large capacitors are typically electrolytic, such as aluminum electrolytic and tantalum electrolytic, because they can produce large capacitance in a smaller physical size. Unfortunately, electrolytic capacitors have poor tolerance, are unipolar (voltage can be applied in only one direction), have poor temperature stability, and have larger internal losses. This last fact equates to large ESRs. Ceramic materials are used for high-frequency capacitors because they perform better in all areas, except that their dielectric constant is lower.
Referring back to Figure 7.4, the frequency response of a capacitor has two distinct regions, which are separated by the resonant frequency. In the low-frequency region, a capacitor behaves like a capacitor, as intended. Its impedance decreases in inverse proportion to frequency. At resonance, the capacitance and the ESL exactly cancel one another, and the impedance is equal to the ESR. In the high-frequency region, a capacitor behaves as an inductor, thus its impedance increases with frequency. As the impedance rises, the capacitor becomes less and less useful as a decoupling device. The inductive reactance of the capacitor at high frequencies causes another, more problematic, effect—antireso-nance. Antiresonance occurs when two or more capacitors with different resonant frequencies are placed in parallel. Consider the case of two capacitors, C1 and C2, that have different capacitances but equal ESL. Capacitor C1, the larger capacitor, has a resonance at frequency, f1, above which it behaves like an inductor. Capacitor C2 has a resonance at a higher frequency, f2, above which it behaves like an inductor. Between these two frequencies, C1 acts like an inductor and C2 acts like a capacitor. At some point in between the two resonant frequencies, antireso-nance occurs. Antiresonance occurs at the parallel resonance of the inductance of C1 and the capacitance of C2. Near this frequency, the impedance rises dramatically, hampering the decoupling ability of the two capacitors. The effect is shown in Figure 12.11.
There are two ways to decrease the height of the anitresonance. The first method is to reduce the frequency gap between the two resonant frequencies. The second method is to use capacitors with higher ESRs. This second method has the side-effect of raising the impedance of the resonance. A balance between the two problems must be found for optimal performance.
The interaction of several capacitors on an actual PCB at high frequencies is not as easy to calculate because the PCB adds its own effects. The traces and vias that connect the decoupling capacitors to the power and ground planes have impedance that is mostly inductive. This inductance further limits the frequency response of the capacitors. Furthermore, the current paths along the power/ground planes themselves cause transmission line effects at high frequency when the distances traversed by the current are electrically long.
To properly model decoupling at high frequencies, the PCB must be included. Therefore, some of the conclusions from studies on decoupling that model only the capacitors themselves cannot be trusted. At low frequencies (when the dimensions of the power/ground planes are less than 1/20), the planes can be modeled as contributing about 0.1nH per inch that a decoupling current travels on the plane. When the planes become electrically large in dimensions, proper modeling takes the form of modeling the power and ground planes as a two-dimensional transmission line. A two-dimensional transmission line has length and width. Signals propagate from their source in two dimensions, as opposed to commonly used transmission lines such as
Figure 12.11 When capacitors of different value are placed in parallel, antiresonant peaks occur. Using two capacitors of the same value produces better results.
Figure 12.11 When capacitors of different value are placed in parallel, antiresonant peaks occur. Using two capacitors of the same value produces better results.
frequency wire pairs that transmit in only one dimension. The capacitor models should include the ESL and ESR. The vias and traces that connect the capacitors to the power/ground planes can be modeled as inductors. The loads can be simulated by using AC or transient current sources that inject current at discrete locations on the PCB. Then the resulting voltage at all points on the plane can be computed to determine the effectiveness of decoupling. If the resulting voltage is lower than the maximum ripple allowed by the components, your design is a success. Spice is often used as the circuit simulation product once the models are created. Such modeling is definitely not required for all PCB products, but such extensive modeling must be used for any high-frequency decoupling studies to have merit. Refer to the papers by I. Novak in the bibliography for more information on accurate power distribution modeling.
Traditionally, decoupling design for digital systems was quite simple. You placed a 0.1 ||F capacitor at each IC, and then included a large bulk capacitance (from 10 ||F to several thousand ||F) somewhere on the board near the power supply. Unfortunately, such simple rules of thumb are not sufficient in digital designs in the hundreds of MHz and higher. Such designs typically have signal rise times less than 1 nsec. Even designs with clock frequencies as low as 30 MHz can cause problems when using the old rules of thumb. Other changes have also affected decoupling. The leading edge microprocessors can have tremendous current surges (10A or more). In addition, the voltages for digital systems have been successively lowered from 5V to 3.3 V to 1.8V and lower. The unfortunate result of lower supply voltage is that the tolerable supply voltage ripple has also been lowered. Whereas in the old days of 5 V TTL logic ICs could handle 500mV of ripple, some of the latest low-voltage technologies can only handle about 50mV of ripple. Thus, there are three reasons why decoupling is becoming more difficult: higher speeds, larger currents, and smaller ripple voltage tolerance.
With all these problems, there are some new technologies that result in better decoupling. The first technology is that of organic semiconductor (OS-CON) electrolytic capacitors. These capacitors combine the high-density capacitance of electrolytic technology with low ESR. Sanyo makes a line of these capacitors. The OS-CON technology produces capacitors with up to thousands of | F that have inductances from 1nH to 5nH and ESRs down to about 0.01ohms. Compared with previous technologies, the ESL is about one quarter that of traditional electrolytic caps and the ESR is about one hundredth that of traditional electrolytic caps. These caps can provide bulk decoupling with much lower impedance.
Advancements have also been made in the technology of capacitors for high frequency. The materials of choice for high-frequency applications are ceramics, such as NPO (a.k.a., C0G) and X7R. The problem for high-frequency capacitors is that of parasitic inductance. New technologies are all aimed at reducing the ESL of high-frequency capacitors. Typical ceramic SMD capacitors are about twice as long as they are wide. SMD capacitors in the size ranges of 0603 to 1210 typically have ESLs in the range of 0.750 nH to 1.250 nH. A simple technical advance for surface mount capacitors is that of swapping length and width. For example, instead of manufacturing capacitors that are 80mils long and 50mils wide (0805), companies are now manufacturing capacitors that are 50mils long and 80mils wide (0508). The wider package gives a wider lead with lower inductance (about 40% lower). Another technology is that of interdigitated capacitors (IDC) and low inductance capacitor arrays (LICA). This technology uses parallel capacitors in an integrated package. The capacitors are arranged such that current flows in opposite directions in adjacent capacitors. The magnetic fields of adjacent capacitors thus tend to cancel each other, resulting in very low inductance, under 1 nH and as low as 50 pH. IDC capacitors use standard SMD mounting, but the LICA caps use leads on the bottom of the package, basically a ball grid array (BGA), to further reduce inductance. AVX (www.avxcorp.com) manufactures such capacitors and provides extensive application notes on these technologies.
The technology of the PCB has also been improved. As a rule, separate power and ground planes are used on modern digital PCBs (and are probably a necessity for systems with clock frequencies above 5 MHz). If placed adjacent to each other in the PCB layer stackup, the two planes can provide charge storage and thus decoupling. Two planes separated by 10mils of FR4 can provide about 50pF per square inch of coupling capacitance, with inductance mostly limited by the vias to the IC leads. Using smaller spacings and higher dielectric constants, capacitance as high as 2.5nF/inch2 can be attained. These techniques are referred to by several names: power plane cores, buried capacitance, or integrated capacitance. Hadco and its subsidiary Zycon are two of the companies that support these technologies.
Because the power/ground planes form a 2D transmission line, reflections and radiation can occur at the edges of the board. Reflections on the power/ground planes limit the effectiveness of the planes for decoupling, mostly because of standing waves. To reduce these effects, discrete resistors or buried resistance strips can be used to connect the power and ground planes along the edge of the PCB. This technique is called dissipative edge termination (DET).
IC manufacturers are also learning that as digital speeds get ever higher, the ICs themselves must have decoupling capacitors integrated onto the chip. On-chip decoupling is a necessity for GHz digital ICs.
There are also layout techniques that can improve high-frequency decoupling performance. Placing the decoupling capacitor as close as possible or underneath the IC on the bottom side of the PCB allows for the highest-frequency performance. This technique reduces the path of the current and reduces inductance. The capacitors should be connected to the IC leads using the shortest and widest traces possible or should be connected directly to the ground and power planes using multiple vias. To achieve the best possible performance, you can use both techniques: connect the capacitor to the IC leads using traces and by using multiple vias to and from the power/ground planes. A single via has a typical inductance of 0.2nH to 0.5nH. A trace on the surface of a PCB has a typical inductance of 20nH/inch to 30nH/inch. By using multiple vias in parallel, and placing the vias as close as possible to the capacitor pads you will get the best results. Some manufacturers even allow vias to be placed inside the pad.
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