Testing the AD Converters Lower Limit Channel

V Modify the circuit by moving the 1 kQ resistor so it connects pin 3 (CH0) and pin 7 (Vss) of the ADC0834. This is shown in the schematic in Figure 1-10 and the wiring diagram in Figure 1-11.

ADC0834

1 kQ

ADC0834

1 kQ

Figure 1-10

Testing The A/D

Converter's Lower Limit Schematic

Figure 1-10

Testing The A/D

Converter's Lower Limit Schematic

Figure 1-11

Testing The A/D Converter's Lower Limit Wiring Diagram

Figure 1-11

Testing The A/D Converter's Lower Limit Wiring Diagram

StampPlot should now display a marching line at the 0 VDC level. If this is what you see, then you have just tested Channel 0 of the A/D converter.

Each channel will display in a different color on the StampPlot graphs.

Channel 2 = Blue

Channel 3 = Green

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